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Espressif Systems /ESP32-S3 /RMT /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH2_TX_END)CH2_TX_END 0 (CH1_TX_ERR)CH1_TX_ERR 0 (CH2_TX_THR_EVENT)CH2_TX_THR_EVENT 0 (CH0_TX_LOOP)CH0_TX_LOOP 0 (CH5_RX_END)CH5_RX_END 0 (CH4_RX_ERR)CH4_RX_ERR 0 (CH6_RX_THR_EVENT)CH6_RX_THR_EVENT 0 (TX_CH3_DMA_ACCESS_FAIL)TX_CH3_DMA_ACCESS_FAIL 0 (RX_CH7_DMA_ACCESS_FAIL)RX_CH7_DMA_ACCESS_FAIL

Description

Masked interrupt status

Fields

CH0_TX_END

The masked interrupt status bit for CH0_TX_END_INT.
CH1_TX_END

The masked interrupt status bit for CH1_TX_END_INT.
CH3_TX_END

The masked interrupt status bit for CH3_TX_END_INT.
CH2_TX_END

The masked interrupt status bit for CH2_TX_END_INT.
CH3_TX_ERR

The masked interrupt status bit for CH3_ERR_INT.
CH0_TX_ERR

The masked interrupt status bit for CH0_ERR_INT.
CH2_TX_ERR

The masked interrupt status bit for CH2_ERR_INT.
CH1_TX_ERR

The masked interrupt status bit for CH1_ERR_INT.
CH0_TX_THR_EVENT

The masked interrupt status bit for CH0_TX_THR_EVENT_INT.
CH3_TX_THR_EVENT

The masked interrupt status bit for CH3_TX_THR_EVENT_INT.
CH1_TX_THR_EVENT

The masked interrupt status bit for CH1_TX_THR_EVENT_INT.
CH2_TX_THR_EVENT

The masked interrupt status bit for CH2_TX_THR_EVENT_INT.
CH2_TX_LOOP

The masked interrupt status bit for CH2_TX_LOOP_INT.
CH3_TX_LOOP

The masked interrupt status bit for CH3_TX_LOOP_INT.
CH1_TX_LOOP

The masked interrupt status bit for CH1_TX_LOOP_INT.
CH0_TX_LOOP

The masked interrupt status bit for CH0_TX_LOOP_INT.
CH6_RX_END

The masked interrupt status bit for CH4_RX_END_INT.
CH4_RX_END

The masked interrupt status bit for CH4_RX_END_INT.
CH7_RX_END

The masked interrupt status bit for CH4_RX_END_INT.
CH5_RX_END

The masked interrupt status bit for CH4_RX_END_INT.
CH5_RX_ERR

The masked interrupt status bit for CH4_ERR_INT.
CH7_RX_ERR

The masked interrupt status bit for CH4_ERR_INT.
CH6_RX_ERR

The masked interrupt status bit for CH4_ERR_INT.
CH4_RX_ERR

The masked interrupt status bit for CH4_ERR_INT.
CH5_RX_THR_EVENT

The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
CH4_RX_THR_EVENT

The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
CH7_RX_THR_EVENT

The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
CH6_RX_THR_EVENT

The masked interrupt status bit for CH4_RX_THR_EVENT_INT.
TX_CH3_DMA_ACCESS_FAIL

The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT.
RX_CH7_DMA_ACCESS_FAIL

The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data